Technical Note
17/18
www.rohm.com
2009.08 - Rev.A
?2009 ROHM Co., Ltd. All rights reserved.
BD9153MUV
?SPAN class="pst BD9153MUV-E2_2471427_7">Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
5. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
6. Input to IC terminals
This is a monolithic IC with P
+
isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 44.
薖-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or
GND>Terminal B (at transistor side); and
薸f GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Fig.44 Simplified structure of monorisic IC
7. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
8 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.15?or less. Note that use of a high DCR
inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified
period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF.
When using an inductor over 0.15? be careful to ensure adequate margins for variation between external devices and
BU9153MUV, including transient as well as static characteristics.
Resistor
Transistor (NPN)
N
N
N
P
+
P
+
P
P substrate
GND
Parasitic element
Pin A
N
N
P
+
P
+
P
P substrate
GND
Parasitic element
EN
C
B
E
N
GND
Pin A
arasiic
element
Pin B
Other adjacent elements
E
B C
GND
arasiic
element
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